The present invention generally relates to an exposure mask and a method for manufacturing a semiconductor device using the same. More specifically, the present invention relates to an exposure mask that can be used in high integration of semiconductor devices and a method for manufacturing a semiconductor device using the same.
Due to development of manufacturing technologies of semiconductor devices, the size of a unit element, e.g., a transistor becomes smaller, and integration of semiconductor devices is increased. In order to develop a highly integrated semiconductor memory device, it is important to reduce the chip size.
In the case of Dynamic Random Access Memory (DRAM) devices, various different methods are used to reduce the chip size. For example, the cell structure is changed, and more specifically, the plane arrangement or layout of active regions is changed.
The general layout of current active regions is an 8F2 structure. The 8F2 structure includes an active region that has a major axis in a horizontal direction and two word lines arranged in parallel to a minor axis of the active region. In the 8F2 structure, the arrangement of the active regions is changed so that the unit cell size may be reduced although the same minimum critical dimension F is applied.
In a DRAM cell that has a folded bit line structure, the 8F2 structure selects one of the two word lines to read data of a cell transistor through one bit line and one sense amplifier (SA).
In the 8F2 layout of the DRAM cell, a space between the active regions is 3F, and it is easy to secure a margin. However, this results in the cell area being increased.
In order to reduce the cell area to smaller than that of the 8F2 layout, an open bit line cell arrangement structure has been developed. When the DRAM cell structure is changed from the 8F2 structure to a 6F2 structure, the cell size is decreased and the chip size is reduced so as to increase the wafer yield. However, a design rule is gradually reduced so that a space between active regions of a semiconductor device is made smaller. As a result, it becomes more difficult to use a photolithography process using a general exposure mask. In order to avoid such a photolithography issue, an assistant feature is formed in a cell edge of the exposure mask to form a device having a reduced design rule.
FIG. 1 is a plane diagram illustrating an edge portion of a conventional exposure mask. FIG. 2 is a plane diagram illustrating a semiconductor device formed using the exposure mask of FIG. 1.
Referring to FIG. 1, the conventional exposure mask comprises shading patterns and assistant features. FIG. 1 shows the edge portion of the exposure mask.
The exposure mask 100 comprises a first region 100A including shading patterns 110 and a second region 100B including assistant features 120. The shading patterns 110 disposed in the first region 100A define photoresist patterns (not shown) of a cell region formed over a semiconductor substrate using photolithography. Hereinafter, the first region 100A of the exposure mask 100 refers to a region where patterns are disposed to define photoresist patterns (not shown) disposed in the cell region of the semiconductor substrate.
The assistant features 120 disposed in the second region 100B are not transferred to the semiconductor substrate after the photolithography. The assistant features 120 are, rather, used to facilitate formation of line patterns of the cell region. It is because the assistant is feature 120 reduces optical proximity effect of the light transmitted formed on the cell region. The second region 100B of the exposure mask 100 refers to a region where the assistant patterns 120 are disposed to facilitate formation of patterns in the cell region of the semiconductor substrate.
The shading pattern 110 has an oblique line shape. More specifically, the shading pattern 110 includes a plurality of line-shaped patterns having an X-axis as a major axis arranged obliquely for optical proximity correction (OPC). The assistant feature 120 has line-shaped patterns having a Y-axis as a major axis. The assistant feature 120 has a width (S1) between line-shaped patterns that is larger than a width (L1) of the line-shaped patterns.
As shown in FIG. 2, a main pattern 210 is transferred onto a semiconductor substrate 200 by using the exposure mask of FIG. 1 having the shading patterns 110 in a photolithography process. The first region 100A of FIG. 1 corresponds to the cell region of the semiconductor substrate. The assistant feature 120 disposed in the second region 100B of FIG. 1 is exposed over the region adjacent to the cell region the semiconductor substrate. As a result, only the main pattern 210 is patterned over the semiconductor substrate. Since the assistant feature 120 has a critical dimension less than resolving power, as result, only a main pattern 210 is pattered on the semiconductor substrate.
A scum 220 having a band type is formed in the edge of the main pattern 210. The scum 220 is generated when the assistant feature 120 disposed in the second region 100B of the exposure mask 100 cannot compensate the optical proximity correction accurately. That is, the assistant feature 120 is not exposed like the shading pattern 110 disposed in the first region 100A of the exposure mask 100, so that the scum 220 is generated in the edge of the main pattern 210. As a result, it is difficult to transfer the shading pattern 110 disposed in the first region 100A of the exposure mask 100 onto the substrate 200 as the shading pattern 120.